FIG. 10 is a block diagram illustrating an example of the part used for driving one line of LEDs on a screen in a general LED display system.
The LED display system shown in FIG. 10 has K (K is an integer of 2 or more) LED drivers U-1, . . . U-K and controller 1 used to control the drivers.
Although not indicated in the figure, the cathodes of the LEDs of the drive objects are connected to the drive signal output terminals Td1-Td16 of LED drivers U-1, . . . , U-K, and the power supply voltage is supplied to the anodes of the LEDs.
LED driver U-k (k is an integer in the range of 1-K) has 16 terminals Td1, . . . Td16 connected to the cathodes of the LEDs, terminal Ta for inputting the on/off control data for the LEDs, terminal Tc for outputting the control data, terminal Tb for inputting clock signal CLK, terminal Tc for inputting latch signal XLAT used for holding the control data, and terminal Tf for outputting an error signal.
K LED drivers U-1-U-K are connected in cascade via terminals Ta and Te. In other words, control data Din output from controller 1 is input to the terminal Ta of LED driver U-1 in the first section. The control data output from the terminal Te of the LED driver in the previous section is input to the terminal Ta of LED drivers U-2-U-K that follow the first section.
Also, clock signal CLK and latch signal XLAT generated by controller 1 are input to LED driver U-k in each section.
In the example shown in FIG. 10, LED driver U-k has flip-flops FF1, . . . , FF16, latch circuits LA1, . . . LA16, drive signal output circuit O1, OR-gate OR1, and transistor Q1.
16 flip-flops FF1-FF16 are connected in cascade between terminals Ta and Te and operate as shift registers. In other words, the control data input to terminal Ta is sequentially shifted from the flip-flop in the first section FF1 to the flip-flop in the final section FF16 connected in cascade synchronously with clock signal CLK and is finally output from terminal Te.
Latch circuit LAi (i is an integer in the range of 1-16) holds the data held in flip-flop FFi synchronously with latch signal XLAT.
In other words, when latch signal XLAT is at the high level, the input data are output directly. When latch signal XLAT changes from the high level to the low level, the data being input are held. When latch signal XLAT is at the low level, the output data are held continuously.
Drive signal output circuit O1 controls the LED drive current flowing to terminal Tdi corresponding to the data held in latch circuit LAi. For example, when the data held in latch circuit LAi is ‘1,’ current for turning on the LED is supplied to output terminal Tdi. When the held data is ‘0,’ the current is cut off to turn off the LED.
Also, drive signal output circuit O1 checks for abnormalities in the drive signal caused by damage to an LED or problems in the current drive circuit for each output channel and, if there are any abnormalities, outputs an error signal Err. Said error signal Err is a 16-bit signal. The bit of the output channel with a detected abnormality goes to the high level.
OR-gate OR1 outputs the logical sum of error signal Err output from the drive signal output circuit. Consequently, if an abnormality is detected in any of the 16 output channels, the output of OR-gate OR1 goes to the high level.
The output signal of OR-gate 1 is input to the base of transistor Q1. The emitter of the transistor is connected to a reference potential line, and its collector is connected to terminal Tf. Consequently, if an abnormality is detected in any of the 16 output channels, transistor Q1 will turn on, and terminal Tf will be connected to the reference potential line.
The terminals Tf of LED drivers U-1-U-16 are connected to a common line L1. The wiring is connected to power supply line Vcc via resistor Ra. Consequently, line L1 is at the high level in the normal state. If an abnormality in the drive signal is detected in any of the output channels of any of the LED drivers, line L1 goes to the low level. Controller 1 detects the abnormality in the drive signal based on the level of line L1.
The LED display system with the configuration shown in FIG. 10 operates as follows.
First, in controller 1, the control data for turning each LED on or off that constitutes a pixel is generated corresponding to the image to be displayed. The generated control data Din is sequentially output from controller 1 synchronously with clock signal CLK. The output control data Din is sequentially shifted in the shift registers comprised of flip-flops FF1-FF16 from the LED driver in the first section U-1 to the final section U-16 connected in cascade. When the desired control data is held in the flip-flops FF1-FF16 of each LED driver as a result of the aforementioned shifting, a high level pulse is output as latch signal XLAT from controller 1. As a result, the control data of flip-flops F1-F16 are held in latch circuits LA1-LA16, and each LED is turned on or off corresponding to the control data.
Also, the level of line L1 is monitored by controller 1. When that level goes low, an abnormality in the drive signal is detected. When an abnormality is detected, for example, details concerning the abnormality are displayed on the display device, and a prescribed process is executed.
However, the error signal transmitted from the LED driver to controller 1 via line L1 indicates only whether there is an output channel with an abnormal drive signal among any of the output channels of any of the LED drivers. It is unable to specify which LED driver or associated output channel has the abnormality by using the aforementioned error signal alone. In order to obtain more specific information about the location of the abnormality, for example, it is necessary to transmit various test signals from controller 1 to investigate the error signal of line L1.
As described above, in the LED display system shown in FIG. 10, it is difficult to obtain the specific information concerning the abnormality of the drive signal of the LED drivers.
In another method, all of the error signals output for each LED driver or its output channel are input into controller 1. In this case, however, when there is a large number of LEDs, the number of the error signals to be checked is also increased, and the number of lines becomes very large.
A general object of the present invention is to solve the aforementioned problems by providing a drive circuit that can efficiently transfer the abnormality of drive signal or other specific information to the external device without increasing the number of lines.
The present invention may also provide a display system that can efficiently obtain the abnormality of drive signal or other specific information from the drive circuits of the display elements while having a simple configuration without increasing the number of lines.